The present invention relates generally to circuitry and protocols associated with operating memory devices, and more particularly to methods for controlling multibank memory devices.
FIG. 1 is a simplified functional block diagram of a memory device 200 that represents any of a wide variety of currently available multibank memory devices. The central memory storage unit is a memory array 202 that is arranged in a plurality of banks, with two such banks 204A and 204B shown. The memory array 202 includes a plurality of individual memory elements (not shown) for storing data, with the memory elements commonly arranged in separately addressable rows and columns, as is well known. Those skilled in the art commonly refer to a collectively addressable subset of the array 202 as a xe2x80x9cpage.xe2x80x9d Typically, a single row of memory elements in a bank of the array constitutes a particular page. In FIG. 1, a plurality of pages 206A and 206B are depicted, corresponding with banks 204A and 204B, respectively.
Particular locations within the memory array 202 are addressable by Address signals that external circuitry such as a memory controller (not shown) provides to the memory device 200. The memory controller also provides a plurality of Control or command signals that are used to designate the particular memory access type and/or sequence of memory accesses. As depicted in FIG. 1, a control/address logic circuit 208 receives the Control and Address signals, which may be provided in parallel signal paths, serially, or some suitable combination. The control/address logic circuit 208 then applies a plurality of internal control signals to control the timing and sequence of operations accessing the banks 204A and 204B via access circuits 210A and 210B, respectively. Those skilled in the art will understand that the depicted access circuits 210A and 210B represent a collection of various functional circuit components commonly found in memory devices. Examples include row and column address latch, buffer, and decoder circuits, sense amplifiers and I/O gating circuitry, and other well-known circuits adapted for particular memory device implementations.
Data written to and read from the memory array 202 is transferred from and to the memory controller or other external circuitry via a data I/O circuit 212 and the access circuits 210A and 210B. Those skilled in the art will also understand that the depicted data I/O circuit 212 represents a collection of various functional circuit components adapted to transmit data to or receive data from external circuitry and to correspondingly receive read data from or transmit write data to the array 202 via the access circuits 210A and 210B.
The memory device 200 depicted in FIG. 1 exemplifies multibank memories such as synchronous dynamic random access memories (SDRAMs) and packet-oriented or synchronous-link DRAMs (known as SLDRAMs). SDRAMs, commonly have two array banks, and SLDRAMs commonly have eight array banks. Providing multiple banks improves the average speed with which a sequence of memory operations can be performed. When access to a particular array bank is complete, a xe2x80x9cprechargexe2x80x9d operation is performed to prepare the corresponding access circuitry for a subsequent data transfer operation with the array bank. The precharge operation requires a certain amount of time for its completion, and therefore limits the speed with which a sequence of memory operations can be performed to a particular array bank. By organizing the memory array to have multiple banks with associated access circuits, the precharge time can, in some instances, be xe2x80x9chidden.xe2x80x9d For example, if a first access is to bank 204A and a subsequent access is to bank 204B, precharge operations associated with bank 204A can occur while executing memory access operations to bank 204B.
Successive memory access operations directed to a single bank ordinarily result in precharge time intervals during which memory access operations cannot be performed. However, if operations are directed to the same page in a given bank (a xe2x80x9cpage hitxe2x80x9d), the successive operations can be performed without precharge. Thus, improving data transfer speed requires detecting the existence of such page hits and interleaving multiple bank and page hit access operations to the memory device 200.
In accordance with the present invention, a method is provided for controlling a multibank memory device. The method includes receiving first, second, and third requests. The first request is applied to the memory and a determination is made as to whether the second request is a page hit. If a page hit, the third request is applied to the memory before the second request. The second request may be temporarily stored or otherwise held, with the second request then being applied to the memory at a determined time following application of the first request.
In one aspect of the invention, a method is provided in connection with a memory controller that receives data transfer requests directed to a multibank memory. The method includes receiving first, second, and third requests, with the second request being directed to a same page as the first request. Execution of the first request is initiated, and the second request is stored. Execution of the third request is then initiated before initiating execution of the second request. The execution of the first request is monitored, and execution of the second request is initiated after execution of the first request has progressed to a predetermined extent. Monitoring the first request may be performed by loading a first address of the first request into a timing chain and successively shifting the first address through a plurality of locations within the timing chain. Execution of the second request may then be initiated after the first address has shifted through a selected one of the timing chain locations. A second address of the second request may then be inserted into the timing chain at the selected location.
In another aspect of the invention, a method is provided in connection with a multibank memory that requires a minimum page time interval between successive registration of commands addressed to the same page in one of the banks. The method includes registering a first command addressed to first page in a first bank. A second command addressed to the first page in the first bank is then held, while a third command addressed to a second bank is registered before elapse of the page time interval. After elapse of the page time interval, the second command is then registered.